Integrated circuits are multi-layer structures produced by applying a sequence of deposition-lithography-etching steps to a semiconductor wafer. In such structures layers have to be precisely aligned with each other, which is controlled by the so-called “overlay measurement”. This measurement is usually accomplished using a box-within-a-box technique consisting of the following. A rectangular frame-like structure is formed in a test site of each layer, and two adjacent layers are considered as being correctly aligned if a specific alignment between the frames on these layers is provided. Overlay defining the alignment is measured by comparing the shifts between the frames at opposite sides: determining whether the frames are precisely concentric, the smaller frame being inside the larger one (in projection).
The above technique is carried out by an ordinary optical microscope, which is capable of measuring line width with a resolution limited by resolution of optical imaging systems, usually not less than several nanometers. The current high-performance semiconductor devices, however, have features' dimensions of 0.13 μm and less, and require measurements of overlay registration with the resolution of less than 1 nm.
A different alignment technique is disclosed in the U.S. Pat. No. 5,216,257. According to this technique, two grating structures of different periodicity are deposited on two adjacent layers in a multi-layer structure, and a change in a moire fringe pattern caused by the superposition of two gratings is detected, being indicative of a grating alignment error.